Ah, that's exactly it! They are good enough for today's applications. They don't provide much incentive to write better applications, though. All of today's general-purpose CPUs are designed to provide maximum performance for one task at a time, because that's how benchmarks are written. Real-world software behaves differently, with multiple tasks pending almost all the time. Processors should be designed to support this environment, and I hope to provide a few ideas on how this can be accomplished.
Please be aware that I'm not really a processor designer, and yes, I know some of these ideas are impractical. Hey, you're getting what you've paid for. :-)
Today's PCs have one or two CPUs in a single functional block, plus one or two banks of DRAM in a separate functional block, creating a bottleneck in the connection between these blocks. Eventually it may be necessary to locate one CPU on the same chip with each memory device to eliminate this bottleneck, but semiconductor vendors are not yet capable of this level of integration. This idea describes a compromise between these two extremes that could be manufactured today, and describes some other generally useful features of MP systems.
Multitasking computers spend a lot of time doing task switching. Given that processor architects will happily add hardware to improve system performance by just a few percentage points, how can we provide hardware acceleration for this function? As a side benefit, this proposal yields significant benefits for interrupt handling.
Code size is an important issue in embedded processor applications. It's possible to reduce code size without inventing new and smaller instruction sets. Like...
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